A MOS transistor generates on/off signals by applying a voltage onto the gate to adjust the current of the channel region. In an existing semiconductor manufacturing technology, in order to improve the performance of MOS transistors, the carrier mobility may be increased by introducing a stress into the channel region. For PMOS transistors, an embedded SiGe technology may be used to generate a compressive stress in the channel region to increase the carrier mobility. The embedded SiGe technology may refer to embedding silicon germanium (SiGe) in the regions where source/drain regions are formed. The crystal lattice mismatch between SiGe and the silicon substrate may generate the compressive stress to the channel region.
The existing embedded SiGe technology for forming a CMOS transistor includes sequentially providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming sidewall spacers on the side surfaces of the gate structure; forming a barrier layer to cover the NMOS transistor; forming trenches in the regions for forming source/drain regions; and forming source/drain regions by filling the trenches with SiGe. Because the crystal lattice constant of SiGe is greater than Si, a compressive stress may be generated in the channel region of the transistor. Therefore, the carrier (holes) mobility may be improved; and the performance of the PMOS transistor may be improved.
The process for forming SiGe in the trenches may be an epitaxial growth process. The density of PMOS transistors in different regions of a semiconductor substrate may be different; and the area density of the source regions and the drain regions of the transistors may be different at different regions of the semiconductor substrate. That is, the area density of the regions for forming SiGe may be different at different regions of the semiconductor substrate. During the epitaxial growth process, the region with a larger area density may consume more reaction gas; and the region with a smaller area density may consume less reaction gas. Further, the reaction gas transformation rate may dominate the rate of the epitaxial growth. Therefore, it may be easy to cause the height of formed SiGe structures in the region with a lower transistor density to be higher than the height of the formed SiGe structures in the region with a higher transistor density, i.e., overfilled; and the uniformity may be poor.
FIG. 1 illustrates existing PMOS transistors having embedded source regions and embedded drain regions. As shown in FIG. 1, the PMOS transistors include a semiconductor substrate 100 having a first region I and a second region II isolated by an isolation structure 101. PMOS transistors are formed in the first region I and the second region II. The density of the PMOS transistors in the first region I is smaller than the density of the PMOS transistors in the second region II. That is, the density of the regions for forming SiGe source/drain regions in the first region I is smaller than the density of the regions for forming SiGe source/drain regions in the second region II. The regions for forming SiGe source/drain regions may be referred as SiGe growth regions. The PMOS transistors also includes gate dielectric layers (not shown) formed on the surface of the semiconductor substrate 100, the gates 102 formed on the gate dielectric layers and the offset spacers 103 formed on the side surfaces of the gate dielectric layers and the gates 102. Further, the PMOS transistors include embedded source/drain regions 104a and the embedded source/drain regions 104b. During the process for forming the PMOS transistor, because the density of the SiGe growth regions may be different at different regions of the semiconductor substrate 100, the height of the embedded source/drain regions 104a in the first region may be greater than the height of the embedded source/drain regions 104b in the second region. That is, the trenches for forming the source regions and the drain regions may be overfilled. Some sorts of over fill still exist in embedded source/drain region 104b in the second region II may be still overfilled although it is not shown in FIG. 1, but the over fill in the second region II is significantly lower than in the first region I.
An ion implantation process may be performed onto the embedded source/drain regions 104a and the embedded source/drain regions 104b; because the height of the embedded source/drain regions 104a in the first region I may be greater than the height of the embedded source/drain regions 104b in the second region II, the ion distribution may be un-uniform. Further, when conductive vias are formed in the source/drain regions 104a and the source/drain regions 104b, the depth of the etching holes for forming the conductive vias may be uneven, thus it may cause the conductive vias to have a higher resistance or a leakage current. Thus, the yield of the PMOS transistors may be relatively low; and the performance of the PMOS transistors may be unacceptable.
The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.